Power semiconductor devices require an efficient edge termination to avoid electric field crowding at the edge of the main contact resulting in breakdown of the device at a relatively low breakdown voltage (VBR). Common power semiconductor devices, such as a pin diode or an insulated-gate bipolar transistor (IGBT) usually have a planar edge termination in order to achieve a breakdown voltage in the range of 80 to 90% of the ideal one-dimensional diode breakdown voltage. Known planar edge termination techniques include junction termination extension (JTE), variation of lateral doping (VLD) layers and floating field ring terminations (FFR) with or without field plate extensions. Another type of edge termination structure is a beveled termination structure. By beveling a defined angle is formed between a lateral p-n junction and the surface of the wafer, and thereby the edge is relieved from high electric fields.
Especially the surface of a semiconductor device is very sensitive to high electric fields. To obtain a well-defined surface and to terminate free bonds at the surface of the wafer a passivation layer stack is formed above the edge termination structure on the surface of the wafer. Semi-insulating and insulating materials are used for the passivation layer structure. Common insulating passivation layers include organic passivation layers such as a silicone rubber layer or a polyimide (PI) layer, and inorganic passivation layers, such as a silicon dioxide (SiO2) layer or glass layers, which consist of SiO2 and additional elements. However, some ions such as sodium (Na) and potassium (K) ions are known to migrate through the oxide layers resulting in instability of the breakdown voltage. To prevent the migration of ions and avoid instability of the breakdown voltage it is known to cover the oxide layers by a silicon nitride (Si3N4) or oxynitride (SiOxNy) layer acting as a diffusion barrier. Undoped silicon dioxide proved to be a brittle material and so phosphorous was added to it to strengthen the material. In addition in phosphosilicate glass (PSG) and boron phosphosilicate glass (BPSG) the phosphorous forms traps for ions and therefore improves the protection provided by the silicon oxide layer against ionic contaminations.
Besides insulating passivation layers semi-insulating layers, such as semi-insulating polycrystalline silicon (SIPOS) layers, are sometimes used as a combined passivation and edge termination. By adjusting the electric conductivity of a semi-insulating layer, a continuous decrease of the potential at the surface can be achieved. The conductivity of a SIPOS layer can be controlled by adjusting its oxygen content.
In power semiconductor modules a silicone gel is often used to protect the power semiconductor chips or wafers from harsh environmental conditions (moisture, in particular) and to provide electrical insulation for high voltage operation. The silicone gel fills all the gaps between the housing of the semiconductor module and the device wafer.
Besides the performance of the power semiconductor devices immediately after the manufacturing process, robustness and long term reliability under environmental conditions of its intended use are of utmost importance. More and more emphasis has been given to robustness and long term stability in high humidity environment. Common stress tests for evaluating the robustness and long term reliability under harsh environmental conditions are the temperature-humidity-bias (THB) test and the highly accelerated temperature and humidity stress test (HAST). As higher the voltage during the test, as higher the degradation acceleration of the passivation and the termination capability. The high electric field in the passivation materials in combination with high temperature and high humidity causes degradation of the materials due to corrosion and sparking events. This leads in the end to an electrical and mechanical degradation of the device termination. For example a silicon nitride layer may react with moisture and get oxidized. During corrosion of the silicon nitride, nitrogen gas is formed which may lift any layer above the silicon nitride layer. Also the corrosion creates a less dense silicon nitride layer with a porous structure resulting in a degraded performance as a passivation layer, as it has a degraded capability filtering the field towards an insulating material, in which a semiconductor device is embedded (exemplarily a gel) and could crack. In case of using aluminum below the silicon nitride layer, humidity may penetrate towards the aluminum through the degenerated silicon nitride layer. The electric field causes that the aluminum corrodes to an aluminum oxide which is growing in mass and cracking the whole termination and passivation structure. The passivation, cannot act anymore properly due to the corrosion and as a result the leakage current is rising until catastrophic breakdown of the power semiconductor device. An additional degradation is caused, when aluminium layers in the termination region like field plates or gate runner grow to aluminium oxide and destroy the passivation above. It needs several hours of high temperature for drying, to get moisture out of the device. With a higher voltage class the electrical field is also stronger and corrosion is accelerated accordingly. For SiC devices, ten times higher fields are allowed in the bulk, as compared to silicon. This imposes difficult challenges especially for SiC power semiconductor devices.
In prior art document US 2014/0061733 A1 there is described a semiconductor device comprising a semiconductor body and a passivation layer stack formed on a surface of the semiconductor body. The passivation layer stack includes an amorphous semi-insulating layer on the surface of the semiconductor body, a first nitride layer on the amorphous semi-insulating layer, an intermediate layer on the first nitride layer and a second nitride layer on the intermediate layer. The intermediate layer may include silicate glass, such as an undoped silicate glass (USG), a phosphorous doped silicate glass (PSG), a boron doped silicate glass (BSG), or a boron and phosphorous doped silicate glass (BPSG). However, there are no means provided in the semiconductor device disclosed in this prior art document which would block flow of humidity towards the top second nitride layer.
In US 2006/226479 A1 a semiconductor device is shown having a passivation layer stack in the following order away from the semiconductor wafer: dielectric layer, silicon glass layer, silicon nitride or oxide layer. The silicon glass layer arranged on top of the dielectric layer neutralizes or reduces the dipole effect or removes surface charges at the interface of the dielectric layer.